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Introduction
As microelectronics technology advances toward miniaturization and heterogeneous integration (e.g., 3D ICs and chiplets), interconnect structures have become a bottleneck for reliability, with emerging failure mechanisms (such as electromigration and thermomechanical fatigue) and material limitations requiring urgent breakthroughs. Industry faces high-cost failures (accounting for over 30% of system failures) and supply chain resilience demands, further highlighted by the release of chiplet interface standards at the 2025 Wuxi Taihu Chip Conference, which exposed gaps in industry standardization. Academically, research lacks multidisciplinary integration, with existing studies often focusing on isolated thermal, electrical, or mechanical effects rather than systematic investigations of new architectures like ultrafine-pitch TSVs and co-packaged optics (CPO).
From a societal perspective, safety-critical applications such as AI computing clusters (e.g., Teco SuperPod 128) and autonomous driving require zero-defect reliability, while CPO technology supports sustainable development by reducing interconnect energy consumption by 50-60%. Recent government and industry initiatives (e.g., China's "Beyond Moore" plan and the U.S. CHIPS Act) and specialized sessions at forums like the 2025 Chengdu High-Reliability Electronic Manufacturing Conference further underscore the urgency of this field.
This special issue aims to bridge interdisciplinary innovation and industry-academia collaboration, providing theoretical foundations and engineering solutions for next-generation electronic systems. Its uniqueness lies in exploring the critical yet understudied intersection of advanced packaging technologies and reliability science, with a dedicated focus on interconnect structures-a domain increasingly recognized as a bottleneck in next-generation electronic systems. While existing literature often emphasizes device-level reliability or broad packaging challenges, this issue delves specifically into the unique failure modes and material-level complexities of interconnects in emerging architectures (e.g., 2.5D/3D ICs, chiplets, and flexible hybrids). Its originality stems from three key aspects as below.
One bridges materials science, mechanical engineering, electrical engineering, and manufacturing perspectives to offer holistic solutions, moving beyond siloed approaches prevalent in current research. Moreover, it prioritizes emerging challenges such as ultrafine-pitch interconnects, high-frequency behavior, and the impact of heterogeneous integration on reliability-topics not yet comprehensively covered in existing publications. By curating insights from both fundamental research and industrial applications, it highlights practical pathways to translate theoretical advances into real-world reliability improvements, catering to the urgent needs of the semiconductor and electronics manufacturing sectors.
This issue will thus serve as a foundational reference for future research and development in packaging interconnect reliability, setting a new benchmark for interdisciplinary collaboration and innovation.
List of topic areas
- Electronic Packaging
- Heterogeneous Integration
- Interconnect Reliability
- Failure Analysis
Submissions Information
Submissions are made using ScholarOne Manuscripts. Registration and access are available at: https://mc.manuscriptcentral.com/ssmt
Author guidelines must be strictly followed. Please see: https://www.emeraldgrouppublishing.com/journal/ssmt#jlp_author_guidelines
Authors should select (from the drop-down menu) the special issue title at the appropriate step in the submission process, i.e. in response to "Please select the issue you are submitting to".
Submitted articles must not have been previously published, nor should they be under consideration for publication anywhere else, while under review for this journal.
Key deadlines
Opening date for manuscripts submissions: 13/10/2025
Closing date for manuscripts submission: 31/07/2026